1. Field of the Invention
This invention relates generally to the testing of digital signal processing units and, more particularly, to the inclusion in the trace data streams of signals identifying selected events in the digital signal processors under test. These selected events are communicated to the testing apparatus by signal groups referred as sync markers.
2. Description of the Related Art
As microprocessors and digital signal processors have become increasingly complex, advanced techniques have been developed to test these devices. Dedicated apparatus is available to implement the advanced techniques. Referring to FIG. 1A, a general configuration for the test and debug of a target processor is shown. The test and debug procedures operate under control of a host processing unit 10. The host processing unit 10 applies control signals to the emulation unit 11 and received (test) data signals from the emulation unit 11 by cable connector 14. The emulation unit 11 applies control signals to and receives (test) signals from the target processing unit 12 by connector cable 15. The emulation unit 11 can be thought of as an interface unit between the host processing unit 10 and the target processor 12. The emulation unit 11 must process the control signals from the host processor unit 10 and apply these signals to the target processor 12 in such a manner that the target processor will respond with the appropriate test signals. The test signals from the target processor 12 can be a variety types. Two of the most popular test signal types are the JTAG (Joint Test Action Group) signals and trace signals. The JTAG signal provides a standardized test procedure in wide use. Trace signals are continuous signals from a multiplicity of junctions in the target processor 12. While the width of the bus interfacing to the host processing unit 10 generally have a standardized width, the bus between the emulation unit 11 and the target processor 12 can be increased to accommodate the increasing complexity of the target processing unit 12. Thus, part of the interface function between the host processing unit 10 and the target processor 12 is to store the test signals until the signals can be transmitted to the host processing unit 10.
Referring to FIG. 1B, the operation of the trigger generation unit 19 is shown. The trigger unit provides the main component by which the operation/state of the target processor can be altered. At least one event signal is applied to the trigger generation unit 19. Based on the identity of the event signal(s) applied to the trigger generation unit 19, a trigger signal is selected. Certain events and combination of events, referred to as an event front, generate a selected trigger signal that results in certain activity in the target processor such as a debug halt. Combinations of different events generating trigger signals are referred to as jobs. Multiple jobs can have the same trigger signal or combination of trigger signals. In the test and debug of the target processor, the trigger signals can provide impetus for changing state in the target processor or for performing a specified activity. The event front defines the reason for the generation of trigger signal. This information is important in understanding the operation of the target processor because, as pointed out above, several combinations of events can result in the generation of a trigger signal. In order to analyze the operation of the target processing unit, the portion of the code resulting in the trigger signal must be identified. However, the events in the host processor leading to the generation of event signals can be complicated. Specifically, the characteristics of an instruction at a program counter address can determine whether a trigger signal should be generated. A trigger signal can be an indication of when an address is within a range of addresses, outside of a range of addresses, some combination of address characteristics, and/or the address is aligned with a reference address. In this instance, the address can be the program address of an instruction or a memory address directly or indirectly referenced by a program instruction.
Trace techniques have assumed an increasing importance in the debug and test of target processors. In this technique, a plurality of streams of information, generally referred to as trace streams, are collected and transferred to the host processing unit for analysis. According to one embodiment of the trace testing technique, a timing stream, a data stream, and program controller stream supply the information. The timing trace stream relates generally to the system clock, the program counter trace stream relates to the executing program, and the data trace stream relates to the results of the executing program. These trace streams are analyzed by the host processor and the activity of the target processor can be reconstructed. The testing by the trace technique is limited by the large amount of data that is transferred from the target processor to host processing unit. The analysis of the target processor is further complicated by the fact that there are periods of processor inactivity. To minimize the transfer of data, the user may wish to avoid providing trace streams for all or selected trace streams during the periods of inactivity. Furthermore, the activity of a processor may be suspended in order to perform an interrupt service routine. It is frequently the situation that an interrupt service routine is known to execute as expected. Once again, the user may wish to eliminate either all of the trace streams associated with the interrupt service routine. When the apparatus includes a pipeline flattener, the interruption of the program execution can result in stored instructions being present in the pipeline flattener. The instructions stored in the pipeline flattener during an interruption of the program execution may or may not be needed for inclusion in the trace stream.
The operation of the target processor involves three states. In the normal code execution state, the execution of normal and interrupt service routines proceed as if there is no test and debug. In secondary code execution, the code is related to a real-time interrupt after a debug event has halted code execution. The central processor code execution is designated as real-time, allowing the service of interrupt designated as real-time after the code execution is halted. The third state involves not running code. No code execution occurs when the emulation functions are enabled, a debug event halts code execution, and no real-time interrupt is being serviced after the code execution is halted. A developer may wish to select during which states the trace data will be transferred to the host processing unit.
A need has been felt for apparatus and an associated method having the feature that selected trace streams can be disabled. It would be a further feature of the apparatus and associated method that selected trace streams can be disabled during a halt in the program execution. It would be yet a further feature of the present apparatus and associated method that selected trace streams can be disabled during an interrupt service routine. It would be a more particular feature of the apparatus and present invention to provide information in the trace streams relating to the instructions stored in the pipeline flattener during interruptions to the program execution.